1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having vertical channels and a method of manufacturing the same.
2. Description of the Related Art
As the length of a channel in a semiconductor device, for example, a field effect transistor (FET), decreases, several characteristics of the FET degrade. For example, short channel effects such as punch-through, drain induced barrier lowering (DIBL), and sub-threshold voltage swing occur. In addition, there are other problems such as an increase in parasitic capacitance (contact capacitance) between a contact region and a substrate, and an increase in leakage current.
In a FET including an active region having vertical channels on a semiconductor substrate, at least one side surface of a fin is used as a channel. A short channel effect can be prevented by an increase in the length of the channel, thereby improving current characteristics. Hereinafter, an active region having a vertical channel is referred to as a fin, and a FET having a fin is referred to as a fin-FET.
FIG. 1A is a plan view of a conventional fin-FET. FIG. 1B is a cross-sectional view of the conventional fin-FET taken along line 1B-1B of FIG. 1.
Referring to FIGS. 1A and 1B, an element isolation layer 20 which defines an active region 12 having vertical channels is formed on a semiconductor substrate 10. A gate electrode 16 covers the active region 12, an element isolation layer 21 is disposed along a minor axis of the active region 12, and an element isolation layer 22 is disposed along a major axis of the active region 12. For convenience, the gate electrodes 16 can be divided into a gate electrode 16a intersecting the active region 12 and a gate electrode 16b intersecting the element isolation layer 22 disposed along the major axis of the active region 12. Reference numeral 18 is an interlayer insulation layer including the gate electrode 16 therein.
The gate electrode 16b intersecting the element isolation layer 22 disposed along the major axis of the active region 12 contacts the sidewall of the active region 12 and is buried in the element isolation layer 22. When electric power is supplied to the buried gate electrode 16b, leakage current is generated in adjacent portions of the active region 12, i.e., portions “a” of the active region 12. The leakage current degrades the refresh characteristics of the memory device.
Fin-FETs in which the gate electrode 16b is not found on the element isolation layer 22 are disclosed are U.S. Pat. No. 6,396,108 and U.S. Pat. No. 6,583,469. In these disclosures, to prevent the formation of the gate electrode 16 on the element isolation layer 22, the gate electrode 16 has a contact shape or bar shape, and thus the gate electrode 16 cannot be formed on the element isolation layer 22 disposed along the major axis of the active region 12.
However, as the design rule decreases, it becomes difficult to form a contact shape or bar shape gate electrode pattern on a substrate. In particular, it is difficult to obtain an overlap margin during a photolithography process in which the gate electrode pattern is formed.